1. Field of the Invention
This invention generally relates to computer-implemented methods, carrier media, and systems for detecting defects on a wafer based on multi-core architecture. Certain embodiments relate to detecting defects on a wafer by comparing output generated by an inspection system for a first of multiple cores to output generated by the inspection system for a second of the multiple cores, which is formed in the same die, different dies, or the same die and different dies on the wafer as the first of the multiple cores.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield in the manufacturing process and thus higher profits. Inspection has always been an important part of fabricating semiconductor devices such as integrated circuits. However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary since even relatively small defects may cause unwanted aberrations in the semiconductor devices.
Many different types of inspection tools have been developed for the inspection of semiconductor wafers. Defect inspection is currently being performed using techniques such as bright field (BF) imaging, dark field (DF) imaging, and scattering. The type of inspection tool that is used for inspecting semiconductor wafers may be selected based on, for example, characteristics of the defects of interest and characteristics of the wafers that will be inspected. For example, some inspection tools are designed to inspect unpatterned semiconductor wafers or patterned semiconductor wafers.
Patterned wafer inspection is of particular interest and importance to the semiconductor industry because processed semiconductor wafers usually have a pattern of features formed thereon. Although inspection of unpatterned wafers, or “monitor wafers.” which have been run through a process tool, may be used as a gauge for the number and types of defects that may be found on patterned wafers, or “product wafers,” defects detected on monitor wafers do not always accurately reflect the defects that are detected on patterned wafers after the same process in the same process tool. Inspection of patterned wafers is, therefore, important to accurately detect defects that may have been formed on the wafer during, or as a result of, processing. Therefore, inspecting patterned wafers or product wafers may provide more accurate monitoring and control of processes and process tools than inspection of monitor wafers.
As design rules shrink, semiconductor manufacturing processes may be operating closer to the limitations on the performance capability of the processes. In addition, smaller defects can have an impact on the electrical parameters of the device as the design rules shrink, which drives more sensitive inspections. Therefore, as design rules shrink, the population of potentially yield relevant defects detected by inspection grows dramatically, and the population of nuisance defects detected by inspection also increases dramatically. Therefore, more and more defects may be detected on the wafers, and correcting the processes to eliminate all of the defects may be difficult and expensive. In some instances, the number of noise and nuisance events detected by an inspection tool can be reduced by using optimized data acquisition parameters and optimized data processing parameters. In addition, the number of noise and nuisance events can be reduced by applying various filtering techniques to the inspection results.
Process variation has been known for a long time to be a limiting factor of inspection sensitivity. Every process exhibits some degree of variation. Process variation can be either controllable or uncontrollable. A controllable variation may become uncontrollable as device scaling reaches a certain point. Process variation can be tolerable (within spec) or intolerable (out-of-spec). Detection of relatively small defects requires suppression of the background noise from both “tolerable” and intolerable variations. In particular, background noise from both types of process variation will decrease the signal-to-noise of defects in inspection output, which can prevent the detection of relatively small defects, thereby reducing the sensitivity of the inspection.
Accordingly, it would be advantageous to develop computer-implemented methods, carrier media, and/or systems for detecting defects on a wafer that can suppress noise from process variations across the wafer thereby increasing the sensitivity of the inspection particularly for relatively small defects.